AArch64 MP+dmb.sy+ctrl-addr-[fr-rf]-data-rfi
"DMB.SYdWW Rfe DpCtrldR DpAddrdR FrLeave RfBack DpDatadW Rfi Fre"
Cycle=Rfi Fre DMB.SYdWW Rfe DpCtrldR DpAddrdR FrLeave RfBack DpDatadW
Relax=
Safe=Rfi Rfe Fre DMB.SYdWW DpAddrdR DpDatadW DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpCtrldR DpAddrdR FrLeave RfBack DpDatadW Rfi Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X6=a; 1:X9=x;
2:X1=a;
}
P0 | P1 | P2 ;
MOV W0,#2 | LDR W0,[X1] | MOV W0,#1 ;
STR W0,[X1] | CBNZ W0,LC00 | STR W0,[X1] ;
DMB SY | LC00: | ;
MOV W2,#1 | LDR W2,[X3] | ;
STR W2,[X3] | EOR W4,W2,W2 | ;
| LDR W5,[X6,W4,SXTW] | ;
| LDR W7,[X6] | ;
| EOR W8,W7,W7 | ;
| ADD W8,W8,#1 | ;
| STR W8,[X9] | ;
| LDR W10,[X9] | ;
Observed
y=1; x=1; a=1; 1:X7=0; 1:X5=1; 1:X10=1; 1:X0=1;
and y=1; x=2; a=1; 1:X7=0; 1:X5=1; 1:X10=1; 1:X0=0;
and y=1; x=1; a=1; 1:X7=0; 1:X5=1; 1:X10=1; 1:X0=0;